module sysgen_hw_cosim_interface(addr, bank_sel, clk, data_in, pci_clk, we, re, data_out);

input [23:0]addr;
input [7:0]bank_sel;
input clk;
input [31:0]data_in;
input pci_clk;
input we;
input re;
output[31:0] data_out;

endmodule

module sysgen_hw_cosim_interface_black_box(addr, bank_sel ,clk ,data_in, pci_clk, we, re, data_out);

input [23:0]addr;
input [7:0]bank_sel;
input clk;
input [31:0]data_in;
input pci_clk;
input we;
input re;
output[31:0]data_out;

sysgen_hw_cosim_interface inst(.addr(addr),
                               .bank_sel(bank_sel),
                               .clk(clk),
                               .data_in(data_in),
                               .pci_clk(pci_clk),
                               .we(we),
                               .re(re),
                               .data_out(data_out));

endmodule